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A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT., , and . J. Real-Time Image Processing, 2 (4): 281-291 (2007)System-level power-performance trade-offs in bus matrix communication architecture synthesis., , , and . CODES+ISSS, page 300-305. ACM, (2006)Thermal sensor allocation for SoCs based on temperature gradients., , and . ISQED, page 29-34. IEEE, (2015)Combined topological and functionality based delay estimation using a layout-driven approach for high level applications., and . EURO-DAC, page 72-78. IEEE Computer Society Press, (1992)FIR filter mapping and performance analysis on MorphoSys., , and . ICECS, page 99-102. IEEE, (2000)Behavioral Modeling of an ATM Switch using SpecCharts., and . VLSI Design, page 19-22. IEEE Computer Society, (1996)An Empirical Study on the Effects of Physical Design in High-Level Synthesis., , , and . VLSI Design, page 11-16. IEEE Computer Society, (1994)Intra-body communication model based on variable biological parameters., , and . ACSSC, page 948-951. IEEE, (2015)Error-aware power management for memory dominated OFDM systems., , , and . ACSSC, page 2034-2040. IEEE, (2013)Rapid in-memory matrix multiplication using associative processor., , , , and . DATE, page 985-990. IEEE, (2018)