Author of the publication

System-level power-performance trade-offs in bus matrix communication architecture synthesis.

, , , and . CODES+ISSS, page 300-305. ACM, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Energy-Aware Adaptations for End-to-End Videostreaming to Mobile Handheld Devices., , , , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 944-951 (2018)Constraint-driven bus matrix synthesis for MPSoC., , and . ASP-DAC, page 30-35. IEEE, (2006)Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs., , and . ASP-DAC, page 497-502. IEEE, (2006)PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures., , and . ASP-DAC, page 491-496. IEEE, (2006)Automated throughput-driven synthesis of bus-based communication architectures., , and . ASP-DAC, page 495-498. ACM Press, (2005)Integrated power management for video streaming to mobile handheld devices., , , , and . ACM Multimedia, page 582-591. ACM, (2003)Regular schedules for scalable design of IIR filters., , and . EURO-DAC, page 52-57. IEEE Computer Society, (1993)Speculation Techniques for High Level Synthesis of Control Intensive Designs., , , , , and . DAC, page 269-272. ACM, (2001)Coordinated transformations for high-level synthesis of high performance microprocessor blocks., , , , , , , and . DAC, page 898-903. ACM, (2002)