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Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study., , , , , и . ICCAD, стр. 1-6. IEEE, (2021)DynGMP: Graph Neural Network-Based Motion Planning in Unpredictable Dynamic Environments., , , , , , и . IROS, стр. 858-865. (2023)VLSI Hardware Architecture of Stochastic Low-rank Tensor Decomposition., , , , и . ACSCC, стр. 1176-1180. IEEE, (2021)IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 373-377. ACM, (2022)MOPED: Efficient Motion Planning Engine with Flexible Dimension Support., , , , и . HPCA, стр. 483-497. IEEE, (2024)VLSI Hardware Architecture of Neural A* Path Planner., , , , и . IEEECONF, стр. 334-338. IEEE, (2022)Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper)., , , и . ICCAD, стр. 104:1-104:7. ACM, (2022)A High Speed CMOS Transmitter and Rail-to-Rail Receiver., , , , , и . DELTA, стр. 67-70. IEEE Computer Society, (2008)Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition With Hierarchical Tucker Tensor Decomposition., , , , и . IEEE Trans. Computers, 71 (12): 3101-3114 (2022)Lightweight design and realisation of autonomously balancing bicycles based on additive manufacturing technology., , , , , , и . Int. J. Comput. Appl. Technol., 71 (2): 89-99 (2023)