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Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework., , , , , , and . ISPD, page 48-55. ACM, (2018)Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code., , , , , and . IEEE Trans. Computers, 71 (4): 933-946 (2022)Area-Driven FPGA Logic Synthesis Using Reinforcement Learning., and . ASP-DAC, page 159-165. ACM, (2023)Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing., , , and . ASP-DAC, page 260-265. ACM, (2021)CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams., and . ASP-DAC, page 616-622. IEEE, (2022)Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation., and . FPL, page 334-340. IEEE, (2021)Design re-use for compile time reduction in FPGA high-level synthesis flows., and . FPT, page 4-11. IEEE, (2014)Generic Connectivity-Based CGRA Mapping via Integer Linear Programming., and . FCCM, page 65-73. IEEE, (2019)Clock gating architectures for FPGA power reduction., , and . FPL, page 112-118. IEEE, (2009)Interconnect capacitance estimation for FPGAs., and . ASP-DAC, page 713-718. IEEE Computer Society, (2004)