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Subleq⊝: An Area-Efficient Two-Instruction-Set Computer., , , и . IEEE Embed. Syst. Lett., 9 (2): 33-36 (2017)EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , и . FPGA, стр. 142-151. ACM, (2019)Clock power reduction for virtex-5 FPGAs., , и . FPGA, стр. 13-22. ACM, (2009)Impact of FPGA architecture on resource sharing in high-level synthesis., , , , , , и . FPGA, стр. 111-114. ACM, (2012)High-level synthesis with LegUp: a crash course for users and researchers., , , и . FPGA, стр. 7-8. ACM, (2013)CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper)., , , , , , , и . ASAP, стр. 156-162. IEEE, (2021)Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays., , , и . ASAP, стр. 242-249. IEEE, (2021)Power Modeling for Heterogeneous Processors., , и . GPGPU@ASPLOS, стр. 90. ACM, (2014)Compact Area and Performance Modelling for CGRA Architecture Evaluation., и . FPT, стр. 126-133. IEEE, (2018)Bitwidth-optimized hardware accelerators with software fallback., и . FPT, стр. 136-143. IEEE, (2013)