( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.

, , , , , , и . IEEE J. Solid State Circuits, 53 (3): 884-895 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

No persons found for author name Talegaonkar, Mrunmay
add a person with the name Talegaonkar, Mrunmay
 

Другие публикации лиц с тем же именем

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS., , , , , и . IEEE J. Solid State Circuits, 49 (10): 2228-2242 (2014)A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links., , , , , и . IEEE J. Solid State Circuits, 50 (12): 3101-3119 (2015)A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time., , , , и . ISSCC, стр. 256-257. IEEE, (2013)A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer., , , , , , и . ISSCC, стр. 152-154. IEEE, (2012)A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS., , и . ISSCC, стр. 360-362. IEEE, (2012)10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS., , , и . ISSCC, стр. 1-3. IEEE, (2015)High Frequency Buck Converter Design Using Time-Based Control Techniques., , , , , , , , и . IEEE J. Solid State Circuits, 50 (4): 990-1001 (2015)Analog Filter Design Using Ring Oscillator Integrators., , и . IEEE J. Solid State Circuits, 47 (12): 3120-3129 (2012)A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS., , , , , , , , и . IEEE J. Solid State Circuits, 52 (9): 2306-2320 (2017)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , и . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)