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Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure.

, , , and . PATMOS, page 237-242. IEEE, (2018)

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An energy-efficient on-chip memory structure for variability-aware near-threshold operation., , and . ISQED, page 23-28. IEEE, (2015)Microarchitectural-level statistical timing models for near-threshold circuit design., , and . ASP-DAC, page 87-93. IEEE, (2015)Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure., , , and . PATMOS, page 237-242. IEEE, (2018)DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification., , , and . ASP-DAC, page 43-49. IEEE, (2022)Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region., , and . LASCAS, page 1-4. IEEE, (2022)A Triturated Sensing System., , , , , , , and . ISSCC, page 216-217. IEEE, (2023)A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication., , , , and . ISSCC, page 218-219. IEEE, (2023)Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics., , , , , and . DAC, page 139-144. IEEE, (2021)A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits., , , and . ACM Trans. Embed. Comput. Syst., 23 (6): 91:1-91:20 (November 2024)Variability- and correlation-aware logical effort for near-threshold circuit design., , and . ISQED, page 18-23. IEEE, (2016)