( en | de | ru )

 

Disambiguation of "Ker, Ming-Dou"

Author of the publication

copydeleteadd this publication to your clipboard
Design considerations and clinical applications of closed-loop neural disorder control SoCs.

, , , , , , , , and . ASP-DAC, page 295-298. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Keqi Dou

Keqi Dou

Wei Dou

Huating Dou

Shouzhi Dou

 

Other publications of authors with the same name

Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications., and . MWSCAS, page 1-4. IEEE, (2018)Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology., and . CICC, page 537-540. IEEE, (1998)Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications., , , and . ISCAS, page 61-64. IEEE, (2000)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., and . SoCC, page 33-36. IEEE, (2013)Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., and . ISCAS (1), page 297-300. IEEE, (2003)Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control., and . VLSI-DAT, page 1-4. IEEE, (2022)Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview.. ICECS, page 325-328. IEEE, (1998)Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard., and . Microelectron. Reliab., 41 (3): 417-429 (2001)New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance., and . IEEE Trans. Ind. Electron., 57 (10): 3533-3543 (2010)Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs., , , and . IEEE J. Solid State Circuits, 46 (2): 537-545 (2011)