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Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Post-bond test of Through-Silicon Vias with open defects., , and . ETS, page 1-6. IEEE, (2014)Defective behaviours of resistive opens in interconnect lines., , and . ETS, page 28-33. IEEE Computer Society, (2005)Diagnosis of full open defects in interconnect lines with fan-out., , , , , and . European Test Symposium, page 233-238. IEEE Computer Society, (2010)Prebond Testing of Weak Defects in TSVs., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1503-1514 (2016)On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data., , , , and . DCIS, page 1-6. IEEE, (2022)Diagnosis of Full Open Defects in Interconnecting Lines., , , , , , , and . VTS, page 158-166. IEEE Computer Society, (2007)Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages., , , , , , , and . VTS, page 145-150. IEEE Computer Society, (2007)Pre-bond testing of weak defects in TSVs., , and . IOLTS, page 31-36. IEEE, (2014)RRAM based cell for hardware security applications., , and . IVSW, page 1-6. IEEE, (2016)