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Simulation of serial RRAM cell based on a Verilog-A compact model.

B. Yang, D. Arumí, S. Manich, Á. Gómez-Pau, R. Rodríguez-Montañés, J. Roldán, M. González, F. Campabadal, and L. Fang. DCIS, page 1-6. IEEE, (2021)

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Michael Salvador

Salvador Herrador

Salvador Oberhaus

Salvador Fernandes

Salvador Millaleo

Other publications of authors with the same name

On High-Quality, Low Energy BIST Preparation at RT-Level.M. Santos, I. Teixeira, J. Teixeira, S. Manich, L. Balado, and J. Figueras. LATW, page 52-57. IEEE, (2002)On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.V. Mahboubi, D. Arumí, Á. Gómez-Pau, R. Rodríguez-Montañés, and S. Manich. DCIS, page 1-6. IEEE, (2022)Improving security in cache memory by power efficient scrambling technique.M. Neagu, L. Miclea, and S. Manich. IET Comput. Digit. Tech., 9 (6): 283-292 (2015)Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.J. Rius, A. Peidro, S. Manich, and R. Rodríguez-Sánchez. PATMOS, volume 2799 of Lecture Notes in Computer Science, page 80-89. Springer, (2003)Design and implementation of Automatic Test Equipment IP module.S. Fransi, G. Farre, L. Garcia-Deiros, and S. Manich. European Test Symposium, page 244. IEEE Computer Society, (2010)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.M. Santos, I. Teixeira, J. Teixeira, S. Manich, R. Rodríguez-Montañés, and J. Figueras. ITC, page 814-823. IEEE Computer Society, (2002)Interleaved scrambling technique: A novel low-power security layer for cache memories.M. Neagu, L. Miclea, and S. Manich. ETS, page 1-2. IEEE, (2014)A Calibratable Detector for Invasive Attacks.M. Weiner, W. Wieser, E. Lupon, G. Sigl, and S. Manich. IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1067-1079 (2019)Low Power BIST by Filtering Non-Detecting Vectors.S. Manich, A. Gabarró, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Teixeira, and M. Santos. J. Electron. Test., 16 (3): 193-202 (2000)Low power BIST by filtering non-detecting vectors.S. Manich, A. Gabarró, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Teixeira, and M. Santos. ETW, page 165-170. IEEE Computer Society, (1999)

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Disambiguation of "Manich, Salvador"

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Simulation of serial RRAM cell based on a Verilog-A compact model.

Please choose a person to relate this publication to

Michael Salvador

Salvador Herrador

Salvador Oberhaus

Salvador Fernandes

Salvador Millaleo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Manich, Salvador"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Simulation of serial RRAM cell based on a Verilog-A compact model.

Please choose a person to relate this publication to

Michael Salvador

Salvador Herrador

Salvador Oberhaus

Salvador Fernandes

Salvador Millaleo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Simulation of serial RRAM cell based on a Verilog-A compact model.