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Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.

, , and . ECCTD, page 592-595. IEEE, (2011)

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Power/throughput/area efficient PIM-based reconfigurable array for parallel processing., , , and . SoCC, page 375-378. IEEE, (2008)Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range., , , , and . WorldCIST (2), volume 354 of Advances in Intelligent Systems and Computing, page 3-9. Springer, (2015)Leakage energy reduction techniques in deep submicron cache memories: a comparative study., , , and . ISCAS, IEEE, (2006)Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology., , and . ICCD, page 499-504. IEEE Computer Society, (2015)Impact of Process Variations on Flip-Flops Energy and Timing Characteristics., , , , and . ISVLSI, page 458-459. IEEE Computer Society, (2010)Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware., , , and . PDP, page 211-218. IEEE Computer Society, (2002)Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor., , , and . FPL, page 13-18. IEEE, (2005)Impact of Random Process Variations on Different 65nm SRAM Cell Topologies., , and . ICETET, page 703-706. IEEE Computer Society, (2010)Designing High-Speed Asynchronous Pipelines., , and . EUROMICRO, page 1394-1399. IEEE Computer Society, (2000)Design of Real-Time FPGA-based Embedded System for Stereo Vision., , , and . ISCAS, page 1-5. IEEE, (2018)