Author of the publication

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.

, , and . ECCTD, page 592-595. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V., , and . ISCAS, page 1-5. IEEE, (2018)Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders., and . ICECS, page 518-521. IEEE, (2006)A closed-form energy model for VLSI circuits under wide voltage scaling., and . ICECS, page 548-551. IEEE, (2016)Energy evaluation in RLC tree circuits with exponential input., , and . ICECS, page 578-581. IEEE, (2008)Analysis of the impact of process variations on static logic circuits versus fan-in., , and . ICECS, page 137-140. IEEE, (2008)Efficient and Accurate Models of Output Transition Time in CMOS Logic., , and . ICECS, page 1264-1267. IEEE, (2007)Analysis of the impact of random process variations in CMOS tapered buffers., , and . ICECS, page 57-60. IEEE, (2009)Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis., , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 624-633. Springer, (2006)Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things., , and . ICECS, page 105-106. IEEE, (2019)Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning., , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1378-1388 (2020)