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A 0.66e-rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique., , , , and . VLSIC, page 84-. IEEE, (2015)A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process., , , , and . ISCAS, page 3594-3597. IEEE, (2007)Session 11 overview: Emerging memory and wireless technology., and . ISSCC, page 190-191. IEEE, (2013)A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing., , , , , and . ISSCC, page 414-415. IEEE, (2013)Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee., and . ISSCC, page 290-291. IEEE, (2012)A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example., , , , and . ASP-DAC, page 821-824. IEEE, (2010)14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A peripheral switchable 3D stacked CMOS image sensor., , , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2010)