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Combinational techniques for sequential equivalence checking.

, , , и . FMCAD, стр. 145-149. IEEE, (2010)

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Robert K Saam

Robert K Müller

Robert K Müller

Robert K Dudler

Robert K G Köhler

 

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Timed Boolean functions - a unified formalism for exact timing analysis., и . The Kluwer international series in engineering and computer science Kluwer, (1994)Verifying Continuous Time Markov Chains., , , и . CAV, том 1102 из Lecture Notes in Computer Science, стр. 269-276. Springer, (1996)VIS: A System for Verification and Synthesis., , , , , , , , , и 6 other автор(ы). CAV, том 1102 из Lecture Notes in Computer Science, стр. 428-432. Springer, (1996)NSF Workshop on EDA: Past, Present, and Future (Part 1)., и . IEEE Des. Test Comput., 27 (2): 68-74 (2010)Explicit and implicit algorithms for binate covering problems., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 677-691 (1997)Theory of safe replacements for sequential circuits., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (2): 249-265 (2001)Exact Required Time Analysis via False Path Detection., и . DAC, стр. 220-225. ACM Press, (1997)Logic Synthesis for Programmable Gate Arrays., , , , и . DAC, стр. 620-625. IEEE Computer Society Press, (1990)Solving the State Assignment Problem for Signal Transition Graphs., , , и . DAC, стр. 568-572. IEEE Computer Society Press, (1992)Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation., , и . DAC, стр. 173-176. IEEE Computer Society Press, (1992)