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Disambiguation of "Murali, Gauthaman"

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Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics.

, , , , , and . VLSI-SOC, page 123-128. IEEE, (2020)

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Aarthi Murali

Murali Sukumaran

Kota Murali

Murali Krishna Bollepalli

NULL Murali Dama

 

Other publications of authors with the same name

RTL-to-GDS Design Tools for Monolithic 3D ICs., , , , , , , , , and . ICCAD, page 126:1-126:8. IEEE, (2020)Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse., , , , , , , , , and 5 other author(s). DAC, page 178. ACM, (2019)ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs., , , , , , and . ICCAD, page 1-9. IEEE, (2021)Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies., and . DATE, page 146-151. IEEE, (2021)Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics., , , , , and . VLSI-SOC, page 123-128. IEEE, (2020)Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics., , , , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 323-341. Springer, (2020)Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs., , , and . ISLPED, page 1-6. ACM, (2024)A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4575-4586 (2022)ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs., , , , and . ISPD, page 97-104. ACM, (2022)3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators., , , and . ICCAD, page 1-9. IEEE, (2023)