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A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4575-4586 (2022)

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Partitioning and placement for buildable QCA circuits., , and . ASP-DAC, page 424-427. ACM Press, (2005)Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches., , , and . Microprocess. Microsystems, (2016)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2331-2335 (July 2023)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . CoRR, (2020)Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 565-569 (2009)FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning., , , and . ISPD, page 93-101. ACM, (2024)ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs., , , , , , and . ICCAD, page 1-9. IEEE, (2021)On Advancing Physical Design Using Graph Neural Networks., and . ICCAD, page 2:1-2:7. ACM, (2022)A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node., , , and . ISLPED, page 1-6. IEEE, (2023)3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs., , , , , and . ISLPED, page 19:1-19:6. ACM, (2022)