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Disambiguation of "Brezzo, Bernard"

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Database Analytics: A Reconfigurable-Computing Approach.

, , , , , , and . IEEE Micro, 34 (1): 19-29 (2014)

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Dirk Bernard

Bernard Andreae

Bernard Broermann

Bernard Willkofer

Bernard Schmidtmann

 

Other publications of authors with the same name

High-Throughput, Lossless Data Compresion on FPGAs., , , and . FCCM, page 113-116. IEEE Computer Society, (2011)Database analytics acceleration using FPGAs., , , , , , , and . PACT, page 411-420. ACM, (2012)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)A Hardware/Software Approach for Database Query Acceleration with FPGAs., , , , , , and . Int. J. Parallel Program., 43 (6): 1129-1159 (2015)Efficient in-system RTL verification and debugging using FPGAs (abstract only)., , , , , and . FPGA, page 269. ACM, (2012)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , and . FPGA, page 153-162. ACM, (2012)Large Payload Streaming Database Sort and Projection on FPGAs., , , , , , and . SBAC-PAD, page 25-32. IEEE Computer Society, (2013)Database Analytics: A Reconfigurable-Computing Approach., , , , , , and . IEEE Micro, 34 (1): 19-29 (2014)TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip., , , , , , , , , and 8 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1537-1557 (2015)Single-chip 4×500-MBd CMOS transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (12): 2004-2014 (1996)