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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , and . CICC, page 1-4. IEEE, (2015)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI., , , , , , , , , and 1 other author(s). ISSCC, page 56-57. IEEE, (2016)A High-Resolution Minimicroscope System for Wireless Real-Time Monitoring., , , , , , and . IEEE Trans. Biomed. Eng., 65 (7): 1524-1531 (2018)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , and 4 other author(s). CICC, page 1-4. IEEE, (2013)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , and . FPGA, page 153-162. ACM, (2012)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)Designing a Testable System on a Chip., , , , , , , , , and 5 other author(s). VTS, page 2-7. IEEE Computer Society, (1998)A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 213-222. IEEE, (2006)