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Disambiguation of "Ha, Yajun"

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Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree.

, , and . ISVLSI, page 55-60. IEEE, (2019)

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Yajun Fang

Yajun Xiao

Yajun Cheng

Hoang Ha

Hoang Ha

 

Other publications of authors with the same name

A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor., , , and . A-SSCC, page 301-304. IEEE, (2014)An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials., , and . ASP-DAC, page 210-215. IEEE, (2009)Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA., , , , and . FPL, page 92-97. IEEE, (2007)An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects., , and . FPL, page 615-618. IEEE, (2008)Criticality-based routing for FPGAS with reverse body bias switch box architectures., , and . FPL, page 1-6. IEEE, (2013)Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs., , , and . FPT, page 53-56. IEEE, (2012)Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA., , , and . FPT, page 365-368. IEEE, (2010)An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 253-265 (January 2023)DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return., , , , and . IEEE Trans. Computers, 70 (5): 803-816 (2021)Vt balancing and device sizing towards high yield of sub-threshold static logic gates., , , and . ISLPED, page 355-358. ACM, (2007)