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From software threads to parallel hardware in high-level synthesis for FPGAs.

, , и . FPT, стр. 270-277. IEEE, (2013)

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Recursive circuit clustering for minimum delay and area., и . FPGA, стр. 242. ACM, (2003)Constrained clock shifting for field programmable gate arrays., и . FPGA, стр. 121-126. ACM, (2002)Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices., , , и . FPL, том 2438 из Lecture Notes in Computer Science, стр. 232-241. Springer, (2002)From C to Blokus Duo with LegUp high-level synthesis., , , , , , , , , и 2 other автор(ы). FPT, стр. 486-489. IEEE, (2013)Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware., , и . FPT, стр. 152-159. IEEE, (2015)FPGA and CPLD Architectures: A Tutorial., и . IEEE Des. Test Comput., 13 (2): 42-57 (1996)The NUMAchine Multiprocessor., , , , , , , , , и 8 other автор(ы). ICPP, стр. 487-496. IEEE Computer Society, (2000)Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems., , , , , и . FCCM, стр. 17-24. IEEE Computer Society, (2012)Improving FPGA Routing Architectures Using Architecture and CAD Interactions., , и . ICCD, стр. 99-104. IEEE Computer Society, (1992)Two-stage physical synthesis for FPGAs., , и . CICC, стр. 171-178. IEEE, (2005)