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Disambiguation of "Hashimoto, Masanori"

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GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction.

, , , , and . IUI, page 173-178. ACM, (2017)

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Setsuko Hashimoto

Marcelo Hashimoto

Jujiro Hashimoto

Yoko Hashimoto

 

Other publications of authors with the same name

Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2441-2446 (2010)Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate., and . IEICE Trans. Electron., 102-C (4): 296-302 (2019)Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 724-731 (2007)DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object., , and . MWSCAS, page 1-4. IEEE, (2022)Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons., , , , , , and . IRPS, page 1-6. IEEE, (2023)Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization., , , , , and . ASP-DAC, page 284-290. ACM, (2021)A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design., , and . DAC, page 446-451. ACM Press, (1999)Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction., and . ITC, page 1-8. IEEE, (2020)Stochastic timing error rate estimation under process and temporal variations., , , and . ITC, page 1-10. IEEE, (2015)Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units., , , and . DAC, page 26:1-26:6. ACM, (2018)