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Другие публикации лиц с тем же именем

Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2014)Identification of Feedback Bridging Faults with Oscillation., , и . Asian Test Symposium, стр. 25-. IEEE Computer Society, (1999)Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code., , и . Asian Test Symposium, стр. 163-166. IEEE Computer Society, (2010)New Class of Tests for Open Faults with Considering Adjacent Lines., , , , , , и . Asian Test Symposium, стр. 301-306. IEEE Computer Society, (2009)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , и . Asian Test Symposium, стр. 423-428. IEEE Computer Society, (2002)Reducing Scan Shifts Using Folding Scan Trees., , , , и . Asian Test Symposium, стр. 6-11. IEEE Computer Society, (2003)Practical Fault Coverage of Supply Current Tests for Bipolar ICs., , , и . DELTA, стр. 189-194. IEEE Computer Society, (2004)On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure., , , , и . DELTA, стр. 269-274. IEEE Computer Society, (2004)Current Testable Design of Resistor String DACs., , , , и . ATS, стр. 399-403. IEEE, (2007)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , и . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)