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New Class of Tests for Open Faults with Considering Adjacent Lines.

, , , , , , и . Asian Test Symposium, стр. 301-306. IEEE Computer Society, (2009)

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Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Okamuro

Hiroyuki Takada

Hiroyuki Isobe

 

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Resynthesis for sequential circuits designed with a specified initial state., , и . VTS, стр. 152-157. IEEE Computer Society, (1995)CMOS open defect detection by supply current test., , , и . DATE, стр. 509. IEEE Computer Society, (2001)A BIST Circuit for IDDQ Tests., , , , , и . Asian Test Symposium, стр. 390-395. IEEE Computer Society, (2003)I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment., , , , , , и . Asian Test Symposium, стр. 112-117. IEEE Computer Society, (2004)On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC., , и . ITC-Asia, стр. 169-174. IEEE, (2019)Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes., , , и . 3DIC, стр. 1-5. IEEE, (2019)Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines., , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2842-2850 (2017)Electrical interconnect test method of 3D ICs by injected charge volume., , , и . 3DIC, стр. TS8.19.1-TS8.19.6. IEEE, (2015)On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects., , , , и . ISCIT, стр. 1-5. IEEE, (2017)Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture., , и . 3DIC, стр. 1-6. IEEE, (2011)