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New Memory Organizations for 3D DRAM and PCMs.

, , , , and . ARCS, volume 7179 of Lecture Notes in Computer Science, page 200-211. Springer, (2012)

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A Multi-core Memory Organization for 3-D DRAM as Main Memory., , , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 62-73. Springer, (2013)Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product., , , , , , , , , and 2 other author(s). ISCA, page 876-889. IEEE, (2024)A Research Retrospective on AMD's Exascale Computing Journey., , , , , , , , , and 61 other author(s). ISCA, page 81:1-81:14. ACM, (2023)Processing-in-Memory: Exploring the Design Space., , , , and . ARCS, volume 9017 of Lecture Notes in Computer Science, page 43-54. Springer, (2015)Design and Analysis of an APU for Exascale Computing., , , , , , , , , and 8 other author(s). HPCA, page 85-96. IEEE Computer Society, (2017)Interconnects in the Third Dimension: Design Challenges for 3D ICs., , , , , , , , , and 1 other author(s). DAC, page 562-567. IEEE, (2007)Toward efficient programmer-managed two-level memory hierarchies in exascale computers., , , , , and . Co-HPC@SC, page 9-16. IEEE, (2014)Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing., , and . MEMSYS, page 506-517. ACM, (2019)Technology, CAD tools, and designs for emerging 3D integration technology., , and . ACM Great Lakes Symposium on VLSI, page 1-2. ACM, (2008)Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 425-437. Springer, (2014)