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Designing Low Power Direct Digital Frequency Synthesizers., , , and . VLSI-SOC, page 105-110. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Systematic design flow for dynamic data management in visual texture decoder of MPEG-4., , , , , , and . ISCAS, IEEE, (2006)Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size., , , , and . ISCAS (2), page 73-76. IEEE, (2003)A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems., , , , and . ISCAS (5), page 129-132. IEEE, (2003)A novel coarse-grain reconfigurable data-path for accelerating DSP kernels., , , , and . FPGA, page 252. ACM, (2004)Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations., , , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1027-1036. Springer, (2002)A full adder based methodology for scaling operation in residue number system., , , , and . ICECS, page 891-894. IEEE, (2002)The low power baseband processing parts of a novel dual mode DECT/GSM terminal., , , , and . ICECS, page 35-38. IEEE, (2001)Designing low-power energy recovery adders based on pass transistor logic., , and . ICECS, page 777-780. IEEE, (2001)HARPA: Solutions for dependable performance under physically induced performance variability., , , , , , , , , and 5 other author(s). SAMOS, page 270-277. IEEE, (2015)