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Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size.

, , , , and . ISCAS (2), page 73-76. IEEE, (2003)

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A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., , and . ISCAS, IEEE, (2006)Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 430-439. Springer, (2003)Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms., , and . J. Embed. Comput., 1 (3): 353-362 (2005)Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic., , , , and . Great Lakes Symposium on VLSI, page 83-88. IEEE Computer Society, (1998)Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications., , , , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 243-254. Springer, (2000)An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform., , , , and . FPL, page 658-661. IEEE, (2005)Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors., , , , , , and . Microelectron. Reliab., 45 (2): 341-348 (2005)The VLSI implementation of a baseband receiver for DECT-based portable applications., , , , , , , , , and . ISCAS (1), page 198-201. IEEE, (1999)An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development., , , , , , , , , and . IPDPS, IEEE Computer Society, (2004)Estimation of power dissipation in glitching using complex-time cellular automata., , , and . ICECS, page 1639-1642. IEEE, (1999)