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Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).

, , , , and . FPGA, page 278. ACM, (2016)

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Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs., and . ACM Trans. Reconfigurable Technol. Syst., 16 (1): 8:1-8:26 (March 2023)Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (12): 2508-2521 (2021)Sit Here: Placing Virtual Machines Securely in Cloud Environments., , and . CLOSER, page 248-259. SCITEPRESS, (2021)FPGA Acceleration of Structured-Mesh-Based Explicit and Implicit Numerical Solvers using SYCL., , , and . IWOCL, page 19:1-19:11. ACM, (2022)FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications., and . ACM Comput. Surv., 51 (4): 72:1-72:39 (2018)Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware., and . DATE, page 1616-1621. IEEE, (2021)Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs.. AHS, page 142-147. IEEE, (2018)A scalable and compact systolic architecture for linear solvers., , and . ASAP, page 186-187. IEEE Computer Society, (2014)Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing., , and . FPL, page 142-147. IEEE, (2005)Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq., and . FCCM, page 202-205. IEEE Computer Society, (2014)