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Memory Access Synchronization in Vector Multiprocessors.

, , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)

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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Hardware Transactional Memory with Operating System Support, HTMOS., , , and . Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 8-17. Springer, (2007)Speculative early register release., , , and . Conf. Computing Frontiers, page 291-302. ACM, (2006)Breaking the bandwidth wall in chip multiprocessors., , , and . ICSAMOS, page 255-262. IEEE, (2011)