( en | de | ru )

 

Disambiguation of "Valero, Mateo"

Author of the publication

copydeleteadd this publication to your clipboard
Breaking the bandwidth wall in chip multiprocessors.

, , , and . ICSAMOS, page 255-262. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Alejandro Valero

Silvia Valero

 

Other publications of authors with the same name

Speculative early register release., , , and . Conf. Computing Frontiers, page 291-302. ACM, (2006)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Breaking the bandwidth wall in chip multiprocessors., , , and . ICSAMOS, page 255-262. IEEE, (2011)Access to streams in multiprocessor systems., , and . PDP, page 310-316. IEEE, (1993)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications., , , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 39-51. Springer, (2011)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)