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Hybrid-Mode Floating-Point FPGA CORDIC Co-processor., , , и . ARC, том 4943 из Lecture Notes in Computer Science, стр. 254-259. Springer, (2008)Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor., , , , и . HPCC, стр. 182-189. IEEE Computer Society, (2008)VLIW coprocessor for IEEE-754 quadruple-precision elementary functions., , , , , , и . ACM Trans. Archit. Code Optim., 10 (3): 12:1-12:22 (2013)A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications., и . ASP-DAC, стр. 523-528. IEEE Computer Society, (2007)Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources., , и . ACM Great Lakes Symposium on VLSI, стр. 343-344. ACM, (2013)Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA., , , и . ICESS, стр. 616-620. IEEE Computer Society, (2008)Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware., , и . ARC, том 4419 из Lecture Notes in Computer Science, стр. 110-121. Springer, (2007)Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining., , , и . Asia-Pacific Computer Systems Architecture Conference, том 4186 из Lecture Notes in Computer Science, стр. 567-573. Springer, (2006)