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O test scheme and adaptive refresh considering temperature distribution.

K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu, H. Yu, J. Jung, K. Nam, S. Choi, J. Lee, U. Kang, Y. Sohn, J. Choi, C. Kim, S. Jang, and G. Jin. ISSCC, page 316-317. IEEE, (2016)

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Johann Söhn

Ewald Söhn

Sigrid Sohn

Melanie Sohn

Elke Sohn

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An Architecture of Sparse Length Sum Accelerator in AxDIMM.S. Kang, B. Kim, S. Lee, and K. Sohn. AICAS, page 1-4. IEEE, (2022)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.S. Lee, S. Kang, J. Lee, H. Kim, E. Lee, S. Seo, H. Yoon, S. Lee, K. Lim, H. Shin and 6 other author(s). ISCA, page 43-56. IEEE, (2021)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.C. Oh, K. Chun, Y. Byun, Y. Kim, S. Kim, Y. Ryu, J. Park, S. Kim, S. uhn Cha, D. Shin and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)An FPGA-based RNN-T Inference Accelerator with PIM-HBM.S. Kang, S. Lee, B. Kim, H. Kim, K. Sohn, N. Kim, and E. Lee. FPGA, page 146-152. ACM, (2022)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture.S. Choi, K. Sohn, and H. Yoo. IEEE J. Solid State Circuits, 40 (1): 254-260 (2005)The Breakthrough Memory Solutions for Improved Performance on LLM Inference.B. Kim, S. Cha, S. Park, J. Lee, S. Lee, S. Kang, J. So, K. Kim, J. Jung, J. Lee and 13 other author(s). IEEE Micro, 44 (3): 40-48 (May 2024)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control.S. Choi, K. Sohn, H. Kim, J. Kim, S. Song, N. Cho, J. Yoo, and H. Yoo. SoC, page 1-4. IEEE, (2006)Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow.S. Hong, W. Jo, S. Kim, S. Kim, K. Sohn, and H. Yoo. VLSI Technology and Circuits, page 1-2. IEEE, (2024)

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Disambiguation of "Sohn, Kyomin"

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18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

Please choose a person to relate this publication to

Johann Söhn

Ewald Söhn

Sigrid Sohn

Melanie Sohn

Elke Sohn

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sohn, Kyomin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

Please choose a person to relate this publication to

Johann Söhn

Ewald Söhn

Sigrid Sohn

Melanie Sohn

Elke Sohn

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.