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O test scheme and adaptive refresh considering temperature distribution.

K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu, H. Yu, J. Jung, K. Nam, S. Choi, J. Lee, U. Kang, Y. Sohn, J. Choi, C. Kim, S. Jang, and G. Jin. ISSCC, page 316-317. IEEE, (2016)

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Ah-Reum Oh

Renate Reum

Anika Reum

Willy Reum

Torsten Reum

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Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.R. Oh, B. Lee, S. Shin, W. Bae, H. Choi, I. Song, Y. Lee, J. Choi, C. Kim, S. Jang and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)All digital on-chip temperature sensor using dual ring oscillators.J. Jang, J. Kim, R. Oh, and M. Sung. ICECS, page 181-184. IEEE, (2013)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.Y. Kim, H. Kim, J. Choi, M. Ahn, D. Lee, S. Cho, D. Park, Y. Park, M. Jang, Y. Kim and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm.S. Hong, D. Kim, J. Lee, R. Oh, C. Yoo, S. Hwang, and J. Lee. CoRR, (2023)A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL.D. Kwon, H. Jeong, J. Choi, W. Kim, J. Kim, J. Yoon, J. Choi, S. Lee, H. Rie, J. Lee and 14 other author(s). ISSCC, page 412-413. IEEE, (2023)3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.S. Lee, K. Lee, M. Sung, M. Alian, C. Kim, W. Cho, R. Oh, S. O, J. Ahn, and N. Kim. PACT, page 22:1-22:12. ACM, (2018)Design and verification of an all-digital on-chip process variation sensor.R. Oh, J. Jang, and M. Sung. ISCAS, page 1684-1687. IEEE, (2013)Multi-object tracking system using dissimilar apparatus in video sequence.A. Oh, J. Lee, J. Lee, S. Moon, D. Nam, and W. Yoo. ICTC, page 1528-1530. IEEE, (2020)A Study on the Improvement of Fine-grained Ship Classification through Data Augmentation Using Generative Adversarial Networks.S. Moon, J. Lee, J. Lee, A. Oh, D. Nam, and W. Yoo. ICTC, page 1230-1232. IEEE, (2021)

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18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

Please choose a person to relate this publication to

Ah-Reum Oh

Renate Reum

Anika Reum

Willy Reum

Torsten Reum

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Oh, Reum"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.

Please choose a person to relate this publication to

Ah-Reum Oh

Renate Reum

Anika Reum

Willy Reum

Torsten Reum

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.