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18.2 A 4x64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter., , , , , , , , and . ISSCC, page 340-342. IEEE, (2024)A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 57 (3): 757-766 (2022)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)Methodology for on-chip adaptive jitter minimization in phase-locked loops., , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (11): 870-878 (2003)An on-die all-digital power supply noise analyzer with enhanced spectrum measurements., , , and . ESSCIRC, page 251-254. IEEE, (2014)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)Design considerations for low-power receiver front-end in high-speed data links., , , , and . CICC, page 1-8. IEEE, (2013)A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS., , , , , , , , and . CICC, page 1-2. IEEE, (2021)Strong injection locking of low-Q LC oscillators., , , , , , , and . CICC, page 699-702. IEEE, (2008)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)