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Disambiguation of "Koyanagi, Mitsumasa"

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3D integration technology for 3D stacked retinal chip.

, , , , , , and . 3DIC, page 1-4. IEEE, (2009)

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Other publications of authors with the same name

3D memory chip stacking by multi-layer self-assembly technology., , , , , , , , and . 3DIC, page 1-4. IEEE, (2013)Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature., , , , , , and . 3DIC, page 1-5. IEEE, (2010)High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs., , , , , and . 3DIC, page 1-4. IEEE, (2011)A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface., , , , , , , , , and 45 other author(s). ISSCC, page 422-424. IEEE, (2012)Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications., , , , , , , and . 3DIC, page 1-4. IEEE, (2021)Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding., , , , , and . 3DIC, page 1-4. IEEE, (2023)High density Cu-TSVs and reliability issues., , , , and . 3DIC, page 1-4. IEEE, (2011)Stacked SOI pixel detector using versatile fine pitch μ-bump technology., , , , and . 3DIC, page 1-4. IEEE, (2011)Three-dimensional integration technology and integrated systems., , and . ASP-DAC, page 409-415. IEEE, (2009)Smart Vision Chip Fabricated Using Three Dimensional Integration Technology., , , , , , and . NIPS, page 720-726. MIT Press, (2000)