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Improved multirate sigma-delta architecture., and . ISCAS (1), page 464-467. IEEE, (2001)Time-interleaved multirate sigma-delta modulators., , and . ISCAS (6), page 5581-5584. IEEE, (2005)A new 1.5V linear transconductor with high output impedance in a large bandwidth., , , and . ISCAS (1), page 157-160. IEEE, (2003)The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead., , , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1062-1066. Springer, (2004)Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (1): 41-45 (2009)The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip., , and . ACAC, page 51-56. IEEE Computer Society, (2000)A new compact low-power high slew rate class AB CMOS buffer., , , and . ISCAS (1), page 237-240. IEEE, (2003)A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors., , , and . ISCAS (1), page 671-674. IEEE, (2001)Comparison of programmable linear resistors based on quasi-floating gate MOSFETs., , , , , and . ISCAS, page 1712-1715. IEEE, (2008)A -72 dB @ 2 MHz IM3 CMOS tunable pseudo-differential transconductor., , , , and . ISCAS, page 73-76. IEEE, (2008)