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The Sparse Abstract Machine., , , , , , , and . CoRR, (2022)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)A high-speed, low-power 3D-SRAM architecture., , and . CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation., and . CICC, page 1-5. IEEE, (2013)Understanding sources of inefficiency in general-purpose chips., , , , , , , , and . ISCA, page 37-47. ACM, (2010)Architectural and implementation tradeoffs in the design of multiple-context processors., , and . ISCA, page 435. ACM, (1992)An Evaluation of Directory Schemes for Cache Coherence., , , and . 25 Years ISCA: Retrospectives and Reprints, page 353-362. ACM, (1998)Design principles for packet parsers., , , and . ANCS, page 13-24. IEEE Computer Society, (2013)Beyond the horizon: The next 10x reduction in power - Challenges and solutions., , , , , , , , , and . ISSCC, page 31. IEEE, (2011)A 700-Mb/s/pin CMOS signaling interface using current integrating receivers., and . IEEE J. Solid State Circuits, 32 (5): 681-690 (1997)