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Estimation of delay test quality and its application to test generation.

, , , , , , and . ICCAD, page 413-417. IEEE Computer Society, (2007)

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Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (3): 499-512 (2016)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications., , , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications., , , , , , and . Microelectron. J., (September 2023)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , and . ATS, page 43-48. IEEE, (2019)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , and . PRDC, page 124-129. IEEE, (2019)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)