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Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test.

, , and . PRDC, page 124-129. IEEE, (2019)

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Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , and . IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement., , , , , , , and . IEEE Des. Test, 39 (5): 34-42 (2022)Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling., , and . MCSoC, page 501-507. IEEE, (2023)A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets., , , , , , and . ATS, page 1-5. IEEE, (2020)A High-Performance and P-Type FeFET-Based Non-Volatile Latch., , , , and . ATS, page 1-5. IEEE, (2023)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)