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An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , и . ESSCIRC, стр. 176-179. IEEE, (2015)Clock synthesis design.. ISSCC, стр. 510. IEEE, (2009)Session 18 overview: Full duplex wireless front-ends., , и . ISSCC, стр. 312-313. IEEE, (2017)A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers., , , , , , и . ISSCC, стр. 62-64. IEEE, (2011)A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS., , , , , и . ISSCC, стр. 374-376. IEEE, (2011)New Associate Editor.. IEEE J. Solid State Circuits, 52 (9): 2223 (2017)New Associate Editor.. IEEE J. Solid State Circuits, 53 (5): 1243 (2018)A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors., и . IEEE J. Solid State Circuits, 32 (5): 736-744 (1997)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , и . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS., , , и . ESSCIRC, стр. 336-339. IEEE, (2009)