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Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., and . FPT, page 193-196. IEEE, (2016)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., and . ICCD, page 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., and . ICCAD, page 1-8. ACM, (2019)Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , and . IOLTS, page 232-235. IEEE, (2018)Autonomous temperature control technique in VLSI circuits through logic replication., and . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)Efficient Functional Locking of Behavioral IPs., and . MWSCAS, page 639-642. IEEE, (2020)Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis., , and . ISCAS, page 1-5. IEEE, (2023)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)Investigation and Optimization of Pin Multiplexing in High-Level Synthesis., , and . ACM Great Lakes Symposium on VLSI, page 427-430. ACM, (2018)