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Disambiguation of "Marinissen, Erik Jan"

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DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

, , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)

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Jan-Erik Schmutz

Adhäsions- und Abriebuntersuchungen mittels rasterkraftmikroskopischer Techniken auf der Mikro- und Nanoskala. Uni Münster, (2009)

Nilgün Erikli

Anders Erikson

Jan Erik Spitzley

Jan Erik Eickbohm

 

Other publications of authors with the same name

How Useful are the ITC 02 SoC Test Benchmarks?, and . IEEE Des. Test Comput., 19 (5): 120, 119 (2002)SOC test architecture design for efficient utilization of test bandwidth., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 399-429 (2003)Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis., and . IEEE Des. Test Comput., 25 (3): 206-207 (2008)Conference Reports., , , , , and . IEEE Des. Test Comput., 23 (4): 262-265 (2006)Device-Aware Test for Back-Hopping Defects in STT-MRAMs., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs., , , , , and . ITC, page 1-10. IEEE, (2020)Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints., , , and . ITC, page 1159-1168. IEEE Computer Society, (2002)Defect-Location Identification for Cell-Aware Test., , , , , and . LATS, page 1-6. IEEE, (2019)The role of test protocols in testing embedded-core-based system ICs., and . ETW, page 70-75. IEEE Computer Society, (1999)Challenges in Embedded Memory Design and Test., , , and . DATE, page 722-727. IEEE Computer Society, (2005)