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Time-domain interconnect characterisation flow for appropriate model segmentation., , and . IET Comput. Digit. Tech., 2 (4): 265-274 (2008)Improved Low-Power LDPC FEC for Coherent Optical Systems., , and . ECOC, page 1-3. IEEE, (2017)An Efficient Twin-Precision Multiplier., , and . ICCD, page 30-33. IEEE Computer Society, (2004)Interconnect-Driven Short-Circuit Power Modeling., and . DSD, page 414-421. IEEE Computer Society, (2001)Application-Specific Energy Optimization of General-Purpose Datapath Interconnect., , , and . ISVLSI, page 301-306. IEEE Computer Society, (2011)Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree., , , , , , and . ICECS, page 77-80. IEEE, (2009)Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication., , and . ICECS, page 45-48. IEEE, (2019)Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits., , and . ISLPED, page 245-249. ACM, (1998)Energy-Efficient Soft-Assisted Product Decoders., , , , and . OFC, page 1-3. IEEE, (2019)Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP., and . OFC, page 1-3. IEEE, (2022)