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Disambiguation of "Yoneda, Tomokazu"

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Design and Optimization of Transparency-Based TAM for SoC Test.

, , , , and . IEICE Trans. Inf. Syst., 93-D (6): 1549-1559 (2010)

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Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

 

Other publications of authors with the same name

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation., , , and . ITC, page 1-8. IEEE Computer Society, (2012)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects., and . DATE, page 1366-1369. ACM, (2008)Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses., , , and . ASP-DAC, page 720-725. IEEE Computer Society, (2007)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , and . ETS, page 1-6. IEEE, (2015)Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing., , and . ATS, page 459-462. IEEE, (2007)Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions., , , and . ETS, page 1-6. IEEE, (2017)Test pattern selection to optimize delay test quality with a limited size of test set., , , , and . European Test Symposium, page 260. IEEE Computer Society, (2010)Power-constrained test scheduling for multi-clock domain SoCs., , and . DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)