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Disambiguation of "Yoneda, Tomokazu"

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Design and Optimization of Transparency-Based TAM for SoC Test.

, , , , and . IEICE Trans. Inf. Syst., 93-D (6): 1549-1559 (2010)

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Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

 

Other publications of authors with the same name

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects., and . DATE, page 1366-1369. ACM, (2008)Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses., , , and . ASP-DAC, page 720-725. IEEE Computer Society, (2007)A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation., , , and . ITC, page 1-8. IEEE Computer Society, (2012)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , and . ETS, page 1-6. IEEE, (2015)Test Scheduling for Memory Cores with Built-In Self-Repair., , and . ATS, page 199-206. IEEE, (2007)Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers., , and . DATE, page 231-236. EDA Consortium, San Jose, CA, USA, (2007)Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection., , , , and . ATS, page 52-57. IEEE Computer Society, (2017)Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths., , , and . ATS, page 125-130. IEEE Computer Society, (2008)