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Disambiguation of "Xie, Zhiyao"

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Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS.

, , , and . CoRR, (2024)

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Jian Xie

Yangpei Xie

Lan Xie

Mingliang Xie

Qian Xie

 

Other publications of authors with the same name

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models., , , , , , , , , and 24 other author(s). CoRR, (2024)RouteNet: routability prediction for mixed-size designs using convolutional neural network., , , , , , and . ICCAD, page 80. ACM, (2018)Robustify ML-Based Lithography Hotspot Detectors., , , , and . ICCAD, page 134:1-134:7. ACM, (2022)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization., , , and . CoRR, (2024)Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS., , , and . CoRR, (2024)Preplacement Net Length and Timing Estimation by Customized Graph Neural Network., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4667-4680 (2022)Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model., , , , , , , and . DATE, page 180-185. IEEE, (2019)MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design., , , , , , , and . ICCAD, page 1-9. IEEE, (2023)Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation., , , , , and . ASP-DAC, page 671-677. ACM, (2021)FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs., , , , and . FPGA, page 15-25. ACM, (2023)