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Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit., , , , , and . IRPS, page 1-5. IEEE, (2019)Effects of Far-BEOL anneal on the WLR and product reliability characterization of FinFET process technology., , , , , , , , , and 1 other author(s). IRPS, page 6. IEEE, (2018)A systematic study of gate dielectric TDDB in FinFET technology., , , , , , , , and . IRPS, page 4. IEEE, (2018)Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism., , , , , , , , , and 1 other author(s). IRPS, page 2. IEEE, (2015)End-to-End QoS Monitoring Tool Development and Performance Analysis for NGN., , , , and . APNOMS, volume 4238 of Lecture Notes in Computer Science, page 332-341. Springer, (2006)Reliability characterization of advanced CMOS image sensor (CIS) with 3D stack and in-pixel DTI., , , , , , , , , and 10 other author(s). IRPS, page 3. IEEE, (2018)Scalable and Reliable Overlay Multicast Network for Live Media Streaming., , , , and . PCM (2), volume 3768 of Lecture Notes in Computer Science, page 48-58. Springer, (2005)Optimal design of dummy ball array in wafer level package to improve board level thermal cycle reliability (BLR)., , , , , , , , , and 1 other author(s). IRPS, page 3. IEEE, (2018)