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A high-speed, low-power 3D-SRAM architecture., , and . CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation., and . CICC, page 1-5. IEEE, (2013)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)The Sparse Abstract Machine., , , , , , , and . CoRR, (2022)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators., , , , and . ASPLOS, page 807-820. ACM, (2019)Energy-Performance Tunable Logic., , and . IEEE J. Solid State Circuits, 44 (9): 2554-2567 (2009)CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography., , , , and . IEEE J. Solid State Circuits, 47 (4): 1031-1042 (2012)A 700-Mb/s/pin CMOS signaling interface using current integrating receivers., and . IEEE J. Solid State Circuits, 32 (5): 681-690 (1997)An Evaluation of Directory Schemes for Cache Coherence., , , and . 25 Years ISCA: Retrospectives and Reprints, page 353-362. ACM, (1998)