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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 390-391. IEEE, (2017)

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Chul-Hoon Lee

Jae-Hoon Lee

Song Hoon Lee

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Jeong-Hoon Lee

 

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