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pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang, S. Shin, H. Park, S. Park, Y. Choi, H. Lee, K. Jeon, J. Lee, H. Ahn, K. Kim, J. Kim, S. Chang, H. Hwang, D. Kim, Y. Yoon, S. Hyun, J. Park, Y. Song, Y. Park, H. Kwon, S. Bae, T. Oh, I. Song, Y. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 390-391. IEEE, (2017)

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Chang-Kyo Jeong

Chong-Kyo Lee

Kyo-Il Lee

Chang-Uh Lee

Lee Chang Huan

Other publications of authors with the same name

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction.S. Cho, C. Lee, J. Kwon, and S. Ryu. CICC, page 1-4. IEEE, (2010)Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments.M. Yoon, S. Lee, C. Lee, S. Cho, and W. Ko. ICUFN, page 637-640. IEEE, (2018)Design of a 1-Volt and µ-power SARADC for Sensor Network Application.S. Cho, C. Lee, and J. Song. ISCAS, page 3852-3855. IEEE, (2007)Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced Concrete Slab Using a Discrete Layered Concrete Damage Model.C. Lee, S. Kee, J. Kang, B. Choi, and J. Lee. Sensors, 20 (20): 5838 (2020)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.H. Chi, C. Lee, J. Park, J. Heo, J. Jung, D. Lee, D. Kim, D. Park, K. Kim, S. Kim and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.C. Lee, J. Lee, K. Kim, J. Heo, G. Cha, J. Baek, D. Moon, Y. Eom, T. Kim, H. Cho and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.C. Lee, M. Ahn, D. Moon, K. Kim, Y. Eom, W. Lee, J. Kim, S. Yoon, B. Choi, S. Kwon and 6 other author(s). VLSIC, page 182-. IEEE, (2015)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC.C. Lee, and S. Ryu. IET Circuits Devices Syst., 13 (8): 1277-1283 (2019)

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Disambiguation of "Lee, Chang-Kyo"

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chang-Kyo Jeong

Chong-Kyo Lee

Kyo-Il Lee

Chang-Uh Lee

Lee Chang Huan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Chang-Kyo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chang-Kyo Jeong

Chong-Kyo Lee

Kyo-Il Lee

Chang-Uh Lee

Lee Chang Huan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.