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pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang, S. Shin, H. Park, S. Park, Y. Choi, H. Lee, K. Jeon, J. Lee, H. Ahn, K. Kim, J. Kim, S. Chang, H. Hwang, D. Kim, Y. Yoon, S. Hyun, J. Park, Y. Song, Y. Park, H. Kwon, S. Bae, T. Oh, I. Song, Y. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 390-391. IEEE, (2017)

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Chung-Hye Kim

Hye-On Kim

Hye Suk Kim

Hye-Jeong Kim

Hye-Jung Kim

Other publications of authors with the same name

A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory Interfaces.J. Lee, H. Kim, S. Park, and J. Chun. A-SSCC, page 1-4. IEEE, (2020)23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.H. Kwon, E. Seo, C. Lee, Y. Seo, G. Han, H. Kim, J. Lee, M. Jang, S. Do, S. Cho and 26 other author(s). ISSCC, page 394-395. IEEE, (2017)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.S. Cho, M. Choi, J. Baek, D. An, S. Kim, D. Lee, S. Yang, G. Kang, J. Park, K. Lee and 25 other author(s). ISSCC, page 242-244. IEEE, (2024)A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique.J. Jin, J. Kim, H. Kim, C. Piao, J. Choi, D. Kang, and C. Jung-Hoon. ESSCIRC, page 146-149. IEEE, (2018)A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.S. Bae, Y. Sohn, K. Park, K. Kim, D. Chung, J. Kim, S. Kim, M. Park, J. Lee, S. Bang and 16 other author(s). ISSCC, page 278-279. IEEE, (2008)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.D. Lee, H. Kwon, D. Kwon, J. Baek, C. Cho, S. Kim, D. An, C. Chang, U. Lim, J. Im and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)High speed serial interface for mobile LCD driver IC.H. Jeon, H. Kim, J. Choi, J. Hong, Y. Kim, H. Oh, D. Han, and L. Kim. ISCAS, page 157-160. IEEE, (2008)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.S. Bae, Y. Sohn, T. Oh, S. Kim, Y. Yang, D. Kim, S. Kwak, H. Seol, C. Shin, M. Park and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)

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Disambiguation of "Kim, Hye-Ran"

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chung-Hye Kim

Hye-On Kim

Hye Suk Kim

Hye-Jeong Kim

Hye-Jung Kim

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kim, Hye-Ran"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Chung-Hye Kim

Hye-On Kim

Hye Suk Kim

Hye-Jeong Kim

Hye-Jung Kim

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.