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Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values., , , , и . IEEE Comput. Archit. Lett., 12 (1): 13-16 (2013)Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors., , и . IEEE Trans. Reliab., 62 (1): 238-243 (2013)Fault Tolerant Parallel Filters Based on Error Correction Codes., , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (2): 384-387 (2015)Optimizing the Implementation of SEC-DAEC Codes in FPGAs., , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3538-3542 (2016)An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (1): 211-215 (2018)Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (11): 1933-1943 (2016)DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs., , , , и . Microelectron. Reliab., (2016)Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput., , и . IEEE Trans. Computers, 65 (1): 326-331 (2016)Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes., , и . IEEE Trans. Computers, 65 (9): 2932-2938 (2016)Low Power embedded DRAM caches using BCH code partitioning., , и . IOLTS, стр. 79-83. IEEE Computer Society, (2012)